(In reply to Elliott from comment #94) > Add the Marvell 9183 to the list: > > with intel_iommu=on: > > dmesg |grep dmar ... > [ 0.719878] dmar: DMAR:[DMA Write] Request device [02:00.1] fault addr > fffe0000 > [ 1.034557] dmar: DRHD: handling fault status reg 3 ... > > lspci -nnv > 02:00.0 SATA controller [0106]: Device [1c28:0122] (rev 14) (prog-if 01 > [AHCI 1.0]) > Subsystem: Marvell Technology Group Ltd. Device [1b4b:9183] > > Note, for google: this is the controller embedded in the Plextor m6e M.2 SSD
FWIW, the PCI vendor ID is actually Lite-on. Can you confirm this patch resolves the problem:
--- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3484,6 +3484,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB388_ESD, quirk_dma_func1_alias); +/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c94 */ +DECLARE_PCI_FIXUP_HEADER(0x1c28, 0x0122, quirk_dma_func1_alias);
/* * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
(In reply to Elliott from comment #94)
> Add the Marvell 9183 to the list:
>
> with intel_iommu=on:
>
> dmesg |grep dmar
...
> [ 0.719878] dmar: DMAR:[DMA Write] Request device [02:00.1] fault addr
> fffe0000
> [ 1.034557] dmar: DRHD: handling fault status reg 3
...
>
> lspci -nnv
> 02:00.0 SATA controller [0106]: Device [1c28:0122] (rev 14) (prog-if 01
> [AHCI 1.0])
> Subsystem: Marvell Technology Group Ltd. Device [1b4b:9183]
>
> Note, for google: this is the controller embedded in the Plextor m6e M.2 SSD
FWIW, the PCI vendor ID is actually Lite-on. Can you confirm this patch resolves the problem:
--- a/drivers/ pci/quirks. c pci/quirks. c PCI_FIXUP_ HEADER( PCI_VENDOR_ ID_TTI, 0x0642, PCI_FIXUP_ HEADER( PCI_VENDOR_ ID_JMICRON,
PCI_ DEVICE_ ID_JMICRON_ JMB388_ ESD,
quirk_ dma_func1_ alias); /bugzilla. kernel. org/show_ bug.cgi? id=42679# c94 */ PCI_FIXUP_ HEADER( 0x1c28, 0x0122, quirk_dma_ func1_alias) ;
+++ b/drivers/
@@ -3484,6 +3484,8 @@ DECLARE_
DECLARE_
+/* https:/
+DECLARE_
/*
* A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in