cache-coherency-switching test case has failed on latest TC2 kernel and I was asked us to add delay 50ms, which is the expected delay to be added between writing on to scaling_setspeed and reading the same values from cpuinfo_cur_freq.
[1]At delay 50ms test failed. so I have added delay 1 sec and still test case failed. From QA side add more delay to test case is not accepted. where as after adding 50ms delay test PASS with kernel config CONFIG_ARM_BL_CPUFREQ and FAILED with CONFIG_ARM_VEXPRESS_BL_CPUFREQ.
I request Kernel developers should take this case in to consideration and reduce the latency.
[1]
commit 1a1995d2c83f79dcda130441db3a89e591185b94
Author: Naresh Kamboju <email address hidden>
Date: Sat Dec 8 00:54:51 2012 +0530
we considered cpuinfo_transition_latency and added delay
between writing on to scaling_setspeed and
reading the same values from cpuinfo_cur_freq.
the reasonable amount of delay added is usleep(50000).i.e. 50ms
I would like to conclude this issue from QA,
cache-coherency -switching test case has failed on latest TC2 kernel and I was asked us to add delay 50ms, which is the expected delay to be added between writing on to scaling_setspeed and reading the same values from cpuinfo_cur_freq.
[1]At delay 50ms test failed. so I have added delay 1 sec and still test case failed. From QA side add more delay to test case is not accepted. where as after adding 50ms delay test PASS with kernel config CONFIG_ ARM_BL_ CPUFREQ and FAILED with CONFIG_ ARM_VEXPRESS_ BL_CPUFREQ.
I request Kernel developers should take this case in to consideration and reduce the latency.
I have done experiments with delay vs kernel configs. the details can be found in below speadsheet. /docs.google. com/a/linaro. org/spreadsheet /ccc?key= 0Ai9ggMs8bsGJdG lKZW1JTERJTFk5T DRGdnR4RHQwTHc# gid=0
https:/
Kernel Config Target cpuinfo_max_freq cpuinfo_min_freq cpuinfo_ transition_ latency without-sleep usleep 1000 usleep 50000 usleep 100000 usleep 1000000 usleep 1000000 ARM_VEXPRESS_ BL_CPUFREQ TC2 2400000 350000 1000000 FAILED FAILED FAIL FAIL FAIL FAIL ARM_BL_ CPUFREQ TC2 1000000 100000 1 FAILED FAILED PASS PASS PASS PASS
CONFIG_
CONFIG_
[1] cda130441db3a89 e591185b94
commit 1a1995d2c83f79d
Author: Naresh Kamboju <email address hidden>
Date: Sat Dec 8 00:54:51 2012 +0530
we considered cpuinfo_ transition_ latency and added delay
between writing on to scaling_setspeed and
reading the same values from cpuinfo_cur_freq.
the reasonable amount of delay added is usleep(50000).i.e. 50ms
Signed-off-by: Naresh Kamboju <email address hidden>
diff --git a/bl-agitator/ bl-agitator. c b/bl-agitator/ bl-agitator. c bl-agitator. c bl-agitator. c frequency( struct bl_properties blp, char *
index 4936ad1..992c2d0 100644
--- a/bl-agitator/
+++ b/bl-agitator/
@@ -302,7 +302,7 @@ static int bl_set_
/* DONE: consider cpuinfo_
- usleep(10000);
+ usleep(50000);
curr_freq = strtoul(curr, NULL, 0);
-Naresh Kamboju