gEDA project

drc confused by outline

Bug #775230 reported by Bdale Garbee
10
This bug affects 2 people
Affects Status Importance Assigned to Milestone
gEDA project
Confirmed
Medium
Unassigned
pcb
Confirmed
Medium
Peter Clifton

Bug Description

DRC complains if features are too close to or overlapping "traces" on the outline layer. Please make it possible to exclude the outline layer from DRC.

Tags: drc
Revision history for this message
Peter Clifton (pcjc2) wrote :

Marking this medium priority as:

1. We can do something about it quite eaily.
2. Littering lots of DRC errors can hide real issues

Ideally, we would add a DRC check for various feature to edge distances, but our "outline" layer is only drawn as a center line by convention, not by an enforced rule.

Changed in pcb:
assignee: nobody → Peter Clifton (pcjc2)
status: New → Confirmed
importance: Undecided → Wishlist
importance: Wishlist → Medium
Revision history for this message
Andrew Poelstra (asp11) wrote :

A workaround for now is to add the pcb::skip-drc attribute to the outline layer.

Maybe the fix is to just do this by default on new boards?

Revision history for this message
Bdale Garbee (bdale) wrote : Re: [Bug 775230] Re: drc confused by outline

On Thu, 29 Mar 2012 19:58:38 -0000, Andrew Poelstra <email address hidden> wrote:
> A workaround for now is to add the pcb::skip-drc attribute to the
> outline layer.

That's what I've been doing.

> Maybe the fix is to just do this by default on new boards?

Yes, that would make sense to me.

Bdale

Traumflug (mah-jump-ing)
Changed in geda-project:
importance: Undecided → Medium
status: New → Confirmed
Bert Timmerman (bert-timmerman)
tags: added: drc
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