cache-coherency-switching: failed on TC2

As per the investigation we have found that we need to add delay between write on to set_speed and read from cur_speed.
As a experimental purpose I have compiled kernel with CONFIG_ARM_BL_CPUFREQ=y and disabled CONFIG_ARM_VEXPRESS_BL_CPUFREQ=y.

bl-agitator has been modified as below and All Test PASSED.

--- a/bl-agitator/bl-agitator.c
+++ b/bl-agitator/bl-agitator.c
@@ -302,6 +302,7 @@ static int bl_set_frequency(struct bl_properties blp, char *frequency)

        sysfs_write_file(blp.cpuid, "scaling_setspeed", line, sizeof(line));
        /* TODO: consider cpuinfo_transition_latency before checking */
+ usleep(10000);
        sysfs_read_file(blp.cpuid, "cpuinfo_cur_freq", curr, sizeof(curr));
        curr_freq = strtoul(curr, NULL, 0);

i have noticed that having usleep(10000) works well with CONFIG_ARM_BL_CPUFREQ=y.
but not with CONFIG_ARM_VEXPRESS_BL_CPUFREQ=y. still I am investigating this issue.

I would like to conclude this issue from QA,

cache-coherency-switching test case has failed on latest TC2 kernel and I was asked us to add delay 50ms, which is the expected delay to be added between writing on to scaling_setspeed and reading the same values from cpuinfo_cur_freq.

[1]At delay 50ms test failed. so I have added delay 1 sec and still test case failed. From QA side add more delay to test case is not accepted. where as after adding 50ms delay test PASS with kernel config CONFIG_ARM_BL_CPUFREQ and FAILED with CONFIG_ARM_VEXPRESS_BL_CPUFREQ.

I request Kernel developers should take this case in to consideration and reduce the latency.

I have done experiments with delay vs kernel configs. the details can be found in below speadsheet.
https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0Ai9ggMs8bsGJdGlKZW1JTERJTFk5TDRGdnR4RHQwTHc#gid=0

Kernel Config Target cpuinfo_max_freq cpuinfo_min_freq cpuinfo_transition_latency without-sleep usleep 1000 usleep 50000 usleep 100000 usleep 1000000 usleep 1000000
CONFIG_ARM_VEXPRESS_BL_CPUFREQ TC2 2400000 350000 1000000 FAILED FAILED FAIL FAIL FAIL FAIL
CONFIG_ARM_BL_CPUFREQ TC2 1000000 100000 1 FAILED FAILED PASS PASS PASS PASS

[1]
commit 1a1995d2c83f79dcda130441db3a89e591185b94
Author: Naresh Kamboju <email address hidden>
Date: Sat Dec 8 00:54:51 2012 +0530

    we considered cpuinfo_transition_latency and added delay
    between writing on to scaling_setspeed and
    reading the same values from cpuinfo_cur_freq.
    the reasonable amount of delay added is usleep(50000).i.e. 50ms

    Signed-off-by: Naresh Kamboju <email address hidden>

diff --git a/bl-agitator/bl-agitator.c b/bl-agitator/bl-agitator.c
index 4936ad1..992c2d0 100644
--- a/bl-agitator/bl-agitator.c
+++ b/bl-agitator/bl-agitator.c
@@ -302,7 +302,7 @@ static int bl_set_frequency(struct bl_properties blp, char *

        sysfs_write_file(blp.cpuid, "scaling_setspeed", line, sizeof(line));
        /* DONE: consider cpuinfo_transition_latency before checking */
- usleep(10000);
+ usleep(50000);
        sysfs_read_file(blp.cpuid, "cpuinfo_cur_freq", curr, sizeof(curr));
        curr_freq = strtoul(curr, NULL, 0);

-Naresh Kamboju

From the latest build this test passed.

test log:
-----------
Running cache-coherency-switching ..

Switching to big mode if not already in.
Running /system/bin/boot-a15.sh -c 0
cpu0 is big

Starting bigLITTLE random switcher in the background
spawning thread(s) on specified cpu(s)

Running stressapptest -M 16 --cc_test -s 10
***bl-agitator***
CPU count: 2
CPU0: big freq 2400000 LITTLE freq 350000
CPU1: big freq 2400000 LITTLE freq 350000
Random switcher seed 100 limit 1000
cache-coherency test finished successfully

Kill bigLITTLE switcher BL_AGITATOR_PID 3885
PID_BL_CHECK= 3885
sending SIGTERM BL_AGITATOR_PID 3885
Time elapsed: 0:00:10.1000
Terminated because of SIG 15
cache-coherency-switching : PASS

Linux Kernel:
Linux version 3.7.0-00637-gc747017 (jenkins-build@ip-10-147-141-109) (gcc version 4.7.3 20121205 (prerelease) (Linaro GCC 4.7-2012.11-1~dev) ) #1 SMP Thu Dec 13 22:15:40 UTC 2012

build:
https://snapshots.linaro.org/android/~linaro-android-restricted/vexpress-tc2-isw-jb-gcc47-armlt-stable-open-linaro-android-12.12-iks-release/2/target/product/vexpress/

full log is available at :
https://pastebin.linaro.org/1312/

-Naresh Kamboju