Incorrect parent of self-loop net in automatically generated circuits
Bug #1518631 reported by
Danil Sokolov
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| Workcraft |
Fix Committed
|
Medium
|
Danil Sokolov | ||
Bug Description
It looks like the parent is incorrectly set for the self-loop nets when importing a circuit from Verilog.
As a result an exception is thrown on copy-paste of a gate with a self-loop.
Related branches
| Changed in workcraft: | |
| status: | Confirmed → Fix Committed |
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