Circuit simulation does not respect the environment STG
Bug #1426784 reported by
Danil Sokolov
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| Workcraft |
Fix Committed
|
High
|
Danil Sokolov | ||
Bug Description
When a circuit is simulated it does not take into account the specified environment STG.
This can break the playback of a trace reported by verification tools, because those traces are for the composed STG of a circuit and its environment (e.g. transitions for the circuit inputs can get replicated during the parallel composition).
Related branches
| Changed in workcraft: | |
| status: | In Progress → Fix Committed |
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