| 2023-09-28 15:13:13 |
Heather Lemon |
bug |
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added bug |
| 2023-09-28 15:22:59 |
Heather Lemon |
nominated for series |
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Ubuntu Mantic |
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| 2023-09-28 15:22:59 |
Heather Lemon |
bug task added |
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glibc (Ubuntu Mantic) |
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| 2023-09-28 15:22:59 |
Heather Lemon |
nominated for series |
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Ubuntu Focal |
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| 2023-09-28 15:22:59 |
Heather Lemon |
bug task added |
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glibc (Ubuntu Focal) |
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| 2023-09-28 15:22:59 |
Heather Lemon |
nominated for series |
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Ubuntu Jammy |
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| 2023-09-28 15:22:59 |
Heather Lemon |
bug task added |
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glibc (Ubuntu Jammy) |
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| 2023-09-28 15:23:14 |
Heather Lemon |
glibc (Ubuntu Focal): assignee |
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Heather Lemon (hypothetical-lemon) |
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| 2023-09-28 15:44:26 |
Heather Lemon |
description |
[IMPACT]
This is a continuation of the lp # 2011421
Intel TDX Azure instances are segfaulting due to an error in glibc.
The glibc error is fixed with this patch [1]
[TEST CASE]
Test case requires an azure TDX instance.
Testing instructions from [2] being
getconf -a | grep CACHE
showing non-zero entries for the cache values
[REGRESSION POTENTIAL]
Compatibility impact on applications which invoke CPUID directly.
(they might have to be patched in ways similar to glibc). But at least the glibc patch appears to be working.
[OTHER]
This will affect Mantic, Jammy, Focal
[0] https://azure.microsoft.com/en-us/blog/azure-confidential-computing-on-4th-gen-intel-xeon-scalable-processors-with-intel-tdx/
[1] https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1493622f4f9048ffede3fbedb64695efa49d662a
[2] https://sourceware.org/bugzilla/show_bug.cgi?id=30643#c12 |
[IMPACT]
This is a continuation of the lp # 2011421
Intel TDX Azure instances are segfaulting due to an error in glibc.
The glibc error is fixed with this patch [1]
FYI elaborating on the commit back-port request [1]
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-1-manual.html
19.1 USING THE CPUID INSTRUCTION
Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor
family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction
returns the family, model and (for some processors) a brand string for the processor that executes the instruction.
It also indicates the features that are present in the processor and gives information about the processor’s caches
and TLB.
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID instruc-
tion will cause the invalid opcode exception (#UD) if executed on a processor that does not support it.
To obtain processor identification information, a source operand value is placed in the EAX register to select the
type of information to be returned. When the CPUID instruction is executed, selected information is returned in the
EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values
returned, and example code, see CPUID—CPU Identification in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.pdf
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
pg 217
[TEST CASE]
Test case requires an azure TDX instance.
Testing instructions from [2] being
getconf -a | grep CACHE
showing non-zero entries for the cache values
[REGRESSION POTENTIAL]
Compatibility impact on applications which invoke CPUID directly.
(they might have to be patched in ways similar to glibc). But at least the glibc patch appears to be working.
[OTHER]
This will affect Mantic, Jammy, Focal
[0] https://azure.microsoft.com/en-us/blog/azure-confidential-computing-on-4th-gen-intel-xeon-scalable-processors-with-intel-tdx/
[1] https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1493622f4f9048ffede3fbedb64695efa49d662a
[2] https://sourceware.org/bugzilla/show_bug.cgi?id=30643#c12 |
|
| 2023-09-28 15:45:57 |
Heather Lemon |
description |
[IMPACT]
This is a continuation of the lp # 2011421
Intel TDX Azure instances are segfaulting due to an error in glibc.
The glibc error is fixed with this patch [1]
FYI elaborating on the commit back-port request [1]
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-1-manual.html
19.1 USING THE CPUID INSTRUCTION
Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor
family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction
returns the family, model and (for some processors) a brand string for the processor that executes the instruction.
It also indicates the features that are present in the processor and gives information about the processor’s caches
and TLB.
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID instruc-
tion will cause the invalid opcode exception (#UD) if executed on a processor that does not support it.
To obtain processor identification information, a source operand value is placed in the EAX register to select the
type of information to be returned. When the CPUID instruction is executed, selected information is returned in the
EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values
returned, and example code, see CPUID—CPU Identification in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.pdf
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
pg 217
[TEST CASE]
Test case requires an azure TDX instance.
Testing instructions from [2] being
getconf -a | grep CACHE
showing non-zero entries for the cache values
[REGRESSION POTENTIAL]
Compatibility impact on applications which invoke CPUID directly.
(they might have to be patched in ways similar to glibc). But at least the glibc patch appears to be working.
[OTHER]
This will affect Mantic, Jammy, Focal
[0] https://azure.microsoft.com/en-us/blog/azure-confidential-computing-on-4th-gen-intel-xeon-scalable-processors-with-intel-tdx/
[1] https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1493622f4f9048ffede3fbedb64695efa49d662a
[2] https://sourceware.org/bugzilla/show_bug.cgi?id=30643#c12 |
[IMPACT]
This is a continuation of the lp # 2011421
Intel TDX Azure instances are segfaulting due to an error in glibc.
The glibc error is fixed with this patch [1]
FYI elaborating on the commit back-port request [1]
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-1-manual.html
19.1 USING THE CPUID INSTRUCTION
Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor
family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction
returns the family, model and (for some processors) a brand string for the processor that executes the instruction.
It also indicates the features that are present in the processor and gives information about the processor’s caches
and TLB.
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID instruc-
tion will cause the invalid opcode exception (#UD) if executed on a processor that does not support it.
To obtain processor identification information, a source operand value is placed in the EAX register to select the
type of information to be returned. When the CPUID instruction is executed, selected information is returned in the
EAX, EBX, ECX, and EDX registers. For a complete description of the CPUID instruction, tables indicating values
returned, and example code, see CPUID—CPU Identification in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 2A
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.pdf
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
pg 217
[TEST CASE]
Test case requires an azure TDX instance.
Testing instructions from [2] being
getconf -a | grep CACHE
showing non-zero entries for the cache values
[REGRESSION POTENTIAL]
Compatibility impact on applications which invoke CPUID directly.
[OTHER]
This will affect Mantic, Jammy, Focal
[0] https://azure.microsoft.com/en-us/blog/azure-confidential-computing-on-4th-gen-intel-xeon-scalable-processors-with-intel-tdx/
[1] https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1493622f4f9048ffede3fbedb64695efa49d662a
[2] https://sourceware.org/bugzilla/show_bug.cgi?id=30643#c12 |
|
| 2023-09-28 17:10:34 |
Heather Lemon |
attachment added |
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lp2037661-jammy.debdiff https://bugs.launchpad.net/ubuntu/+source/glibc/+bug/2037661/+attachment/5705174/+files/lp2037661-jammy.debdiff |
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| 2023-09-28 20:18:33 |
Ubuntu Foundations Team Bug Bot |
tags |
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patch |
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| 2023-09-28 20:18:36 |
Ubuntu Foundations Team Bug Bot |
bug |
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added subscriber Ubuntu Sponsors |
| 2023-09-29 15:51:04 |
Heather Lemon |
tags |
patch |
patch ubuntu-sponsors |
|
| 2023-09-29 15:51:21 |
Heather Lemon |
glibc (Ubuntu Jammy): assignee |
|
Heather Lemon (hypothetical-lemon) |
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| 2023-09-29 15:51:23 |
Heather Lemon |
glibc (Ubuntu Mantic): assignee |
|
Heather Lemon (hypothetical-lemon) |
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| 2023-10-02 13:41:44 |
Heather Lemon |
glibc (Ubuntu Focal): status |
New |
Invalid |
|
| 2023-10-03 14:51:33 |
Heather Lemon |
tags |
patch ubuntu-sponsors |
patch |
|
| 2023-10-05 14:51:52 |
Simon Chopin |
glibc (Ubuntu Jammy): importance |
Undecided |
High |
|
| 2023-10-05 14:51:54 |
Simon Chopin |
glibc (Ubuntu Mantic): importance |
Undecided |
High |
|
| 2023-10-05 14:51:58 |
Simon Chopin |
glibc (Ubuntu Jammy): status |
New |
In Progress |
|
| 2023-10-05 14:52:00 |
Simon Chopin |
glibc (Ubuntu Mantic): status |
New |
In Progress |
|
| 2023-10-05 14:52:49 |
Simon Chopin |
glibc (Ubuntu Jammy): assignee |
Heather Lemon (hypothetical-lemon) |
Simon Chopin (schopin) |
|
| 2023-10-05 14:52:52 |
Simon Chopin |
glibc (Ubuntu Mantic): assignee |
Heather Lemon (hypothetical-lemon) |
Simon Chopin (schopin) |
|
| 2023-10-05 14:52:59 |
Simon Chopin |
removed subscriber Ubuntu Sponsors |
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