ubuntu-kernel-tests

msr in ubuntu_kvm_unit_tests fails on Bionic i386

Bug #1916286 reported by Kelsey Steele
6
This bug affects 1 person
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Bug Description

Failures reported on Bionic 4.15 i386
 FAIL msr (294 tests, 208 unexpected failures)

 Running '/home/ubuntu/autotest/client/tmp/ubuntu_kvm_unit_tests/src/kvm-unit-tests/tests/msr'
 BUILD_HEAD=5251136b
 timeout -k 1s --foreground 90s /usr/bin/qemu-system-i386 --no-reboot -nodefaults -device pc-testdev -device isa-debug-exit,iobase=0xf4,iosize=0x4 -vnc none -serial stdio -device pci-testdev -machine accel=kvm -kernel /tmp/tmp.fvRNNVabv3 -smp 1 -cpu max,vendor=GenuineIntel # -initrd /tmp/tmp.lRjxpIRqye
 enabling apic
 smp: waiting for 0 APs
 PASS: MSR_IA32_SYSENTER_CS
 PASS: MSR_IA32_SYSENTER_ESP
 PASS: MSR_IA32_SYSENTER_EIP
 PASS: MSR_IA32_MISC_ENABLE
 PASS: MSR_IA32_CR_PAT
 FAIL: Expected #GP on WRSMR(MSR_FS_BASE, 0x123456789abc), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_FS_BASE), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_GS_BASE, 0x123456789abc), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_GS_BASE), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_KERNEL_GS_BASE, 0x123456789abc), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_KERNEL_GS_BASE), got vector 0
 PASS: MSR_EFER
 FAIL: Expected #GP on WRSMR(MSR_LSTAR, 0x123456789abc), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_LSTAR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_CSTAR, 0x123456789abc), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_CSTAR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_SYSCALL_MASK, 0xffffffff), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_SYSCALL_MASK), got vector 0
 PASS: MSR_IA32_MC0_CTL
 PASS: MSR_IA32_MC0_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC0_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC0_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC0_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC0_ADDR
 PASS: MSR_IA32_MC0_ADDR
 PASS: MSR_IA32_MC0_MISC
 PASS: MSR_IA32_MC0_MISC
 PASS: MSR_IA32_MC0_MISC
 PASS: MSR_IA32_MC1_CTL
 PASS: MSR_IA32_MC1_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC1_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC1_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC1_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC1_ADDR
 PASS: MSR_IA32_MC1_ADDR
 PASS: MSR_IA32_MC1_MISC
 PASS: MSR_IA32_MC1_MISC
 PASS: MSR_IA32_MC1_MISC
 PASS: MSR_IA32_MC2_CTL
 PASS: MSR_IA32_MC2_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC2_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC2_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC2_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC2_ADDR
 PASS: MSR_IA32_MC2_ADDR
 PASS: MSR_IA32_MC2_MISC
 PASS: MSR_IA32_MC2_MISC
 PASS: MSR_IA32_MC2_MISC
 PASS: MSR_IA32_MC3_CTL
 PASS: MSR_IA32_MC3_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC3_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC3_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC3_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC3_ADDR
 PASS: MSR_IA32_MC3_ADDR
 PASS: MSR_IA32_MC3_MISC
 PASS: MSR_IA32_MC3_MISC
 PASS: MSR_IA32_MC3_MISC
 PASS: MSR_IA32_MC4_CTL
 PASS: MSR_IA32_MC4_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC4_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC4_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC4_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC4_ADDR
 PASS: MSR_IA32_MC4_ADDR
 PASS: MSR_IA32_MC4_MISC
 PASS: MSR_IA32_MC4_MISC
 PASS: MSR_IA32_MC4_MISC
 PASS: MSR_IA32_MC5_CTL
 PASS: MSR_IA32_MC5_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC5_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC5_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC5_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC5_ADDR
 PASS: MSR_IA32_MC5_ADDR
 PASS: MSR_IA32_MC5_MISC
 PASS: MSR_IA32_MC5_MISC
 PASS: MSR_IA32_MC5_MISC
 PASS: MSR_IA32_MC6_CTL
 PASS: MSR_IA32_MC6_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC6_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC6_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC6_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC6_ADDR
 PASS: MSR_IA32_MC6_ADDR
 PASS: MSR_IA32_MC6_MISC
 PASS: MSR_IA32_MC6_MISC
 PASS: MSR_IA32_MC6_MISC
 PASS: MSR_IA32_MC7_CTL
 PASS: MSR_IA32_MC7_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC7_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC7_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC7_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC7_ADDR
 PASS: MSR_IA32_MC7_ADDR
 PASS: MSR_IA32_MC7_MISC
 PASS: MSR_IA32_MC7_MISC
 PASS: MSR_IA32_MC7_MISC
 PASS: MSR_IA32_MC8_CTL
 PASS: MSR_IA32_MC8_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC8_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC8_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC8_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC8_ADDR
 PASS: MSR_IA32_MC8_ADDR
 PASS: MSR_IA32_MC8_MISC
 PASS: MSR_IA32_MC8_MISC
 PASS: MSR_IA32_MC8_MISC
 PASS: MSR_IA32_MC9_CTL
 PASS: MSR_IA32_MC9_CTL
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC9_CTL, 0xaaaaaaaaaaaaaaaa), got vector 0
 PASS: MSR_IA32_MC9_STATUS
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC9_STATUS, 0x1), got vector 0
 PASS: MSR_IA32_MC9_ADDR
 PASS: MSR_IA32_MC9_ADDR
 PASS: MSR_IA32_MC9_MISC
 PASS: MSR_IA32_MC9_MISC
 PASS: MSR_IA32_MC9_MISC
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC10_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC10_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC10_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC10_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC10_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC10_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC10_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC10_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC11_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC11_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC11_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC11_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC11_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC11_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC11_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC11_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC12_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC12_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC12_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC12_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC12_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC12_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC12_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC12_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC13_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC13_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC13_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC13_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC13_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC13_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC13_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC13_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC14_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC14_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC14_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC14_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC14_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC14_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC14_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC14_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC15_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC15_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC15_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC15_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC15_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC15_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC15_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC15_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC16_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC16_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC16_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC16_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC16_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC16_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC16_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC16_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC17_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC17_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC17_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC17_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC17_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC17_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC17_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC17_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC18_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC18_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC18_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC18_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC18_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC18_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC18_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC18_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC19_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC19_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC19_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC19_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC19_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC19_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC19_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC19_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC20_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC20_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC20_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC20_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC20_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC20_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC20_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC20_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC21_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC21_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC21_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC21_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC21_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC21_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC21_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC21_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC22_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC22_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC22_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC22_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC22_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC22_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC22_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC22_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC23_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC23_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC23_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC23_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC23_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC23_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC23_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC23_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC24_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC24_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC24_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC24_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC24_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC24_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC24_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC24_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC25_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC25_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC25_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC25_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC25_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC25_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC25_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC25_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC26_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC26_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC26_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC26_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC26_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC26_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC26_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC26_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC27_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC27_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC27_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC27_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC27_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC27_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC27_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC27_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC28_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC28_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC28_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC28_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC28_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC28_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC28_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC28_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC29_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC29_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC29_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC29_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC29_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC29_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC29_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC29_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC30_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC30_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC30_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC30_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC30_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC30_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC30_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC30_MISC, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC31_CTL), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC31_CTL, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC31_STATUS), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC31_STATUS, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC31_ADDR), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC31_ADDR, 0x0), got vector 0
 FAIL: Expected #GP on RDSMR(MSR_IA32_MC31_MISC), got vector 0
 FAIL: Expected #GP on WRSMR(MSR_IA32_MC31_MISC, 0x0), got vector 0
 SUMMARY: 294 tests, 208 unexpected failures
 FAIL msr (294 tests, 208 unexpected failures)

See original description
Kelsey Steele (kelsey-steele)
tags: added: sru-20210315
Revision history for this message
Po-Hsu Lin (cypressyew) wrote :

Found on 5.4.0-84.94~18.04.1 i386

summary: - msr in ubuntu_kvm_unit_tests fails on Bionic
+ msr in ubuntu_kvm_unit_tests fails on Bionic i386
tags: added: sru-20210816
Revision history for this message
Po-Hsu Lin (cypressyew) wrote :

With kvm-unit-test repo updated to d8a4f9e5 (ci: Update the list of tests that we run in the Fedora Cirrus-CI), this test is still failing but the error message is different, I will update the bug description.

description: updated
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