Assign own desing rules to net
Bug #699624 reported by
iikka81
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| gEDA project |
New
|
Wishlist
|
Unassigned | ||
| pcb |
New
|
Wishlist
|
Unassigned | ||
Bug Description
It would be great if each net could have own design rules (DRC). I usually have high voltage circuit and low voltage circuit in a same PCB, and these circuits need different clearances etc.
Revision history for this message
| Ineiev (ineiev) wrote | #1 |
| Changed in geda-project: | |
| importance: | Undecided → Wishlist |
| tags: | added: drc |
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I'm just working on a patchset which will make it possible to assign distinct design rules to every layer, not to every net; however, if you route the net in a dedicated layer, it will be the same (note that I'm speaking about PCB layers which are united in groups to produce single copper layer per group). if you are interested, I can push my work in progress into my GIT repository. currently, it lacks GTK UI (the Lesstif should work; you also can add design rules to PCB manually via external text editor); also, I plan to add distinct design rules for `pad' layers (component and solder).