Automatic VIA during line drawing w/AutoDRC can fail DRC
Bug #699285 reported by
Ben Jackson
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| gEDA project |
New
|
Medium
|
Unassigned | ||
| pcb |
New
|
Undecided
|
Unassigned | ||
Bug Description
If you're drawing a line on one layer and then switch to another layer to continue, PCB inserts the necessary via. Even if AutoDRC is on this via can short another net or simply be too close to it for the design rules.
Revision history for this message
| DJ Delorie (djdelorie) wrote | #1 |
| Changed in geda-project: | |
| importance: | Undecided → Medium |
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What should it do then?