[size] Redundant uxth/sxth insn are generated
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
Linaro GCC |
Triaged
|
Low
|
Kugan Vivekanandarajah |
Bug Description
Compile this case by FSF GCC trunk reveals redundant uxth/sxth instructions.
short unPack( unsigned char c )
{
/* Only want lower four bit nibble */
c = c & (unsigned char)0x0F ;
if( c > 7 ) {
/* Negative nibble */
return( ( short )( c - 16 ) ) ;
}
else
{
/* positive nibble */
return( ( short )c ) ;
}
}
# arm-none-
unPack:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
and r0, r0, #15
cmp r0, #7
bls .L3
subs r0, r0, #16
uxth r0, r0
.L3:
sxth r0, r0
bx lr
uxth/sxth are still there with option {thumb,arm} {O2,O3}
tags: | added: size task |
Changed in gcc-linaro: | |
assignee: | nobody → Kugan Vivekanandarajah (kugan-vivekanandarajah) |
It is found in eembc/automotiv e/idctrn01/ bmark.c