vldr/vstr s0,[r0,r1] not rejected; assembles w/out warning as vldr/vstr s0,[r0]

The assembler accepts without any warning or error message VSTR and VLDR instructions with the memory addressing mode of [Rn, Rm]. This memory addressing mode does not exist for these instructions, as the modes are limited to [Rn] and [Rn, #imm] in the Cortex-M4. But the assembler accepts them anyway in this example code, but then produces code that ignores the Rm index register.

  .syntax unified
  .cpu cortex-m4
  .text

  .global test
  .thumb_func
  .align
test:
  vldr s0, [r0,r1] // disassembles as vldr s0, [r0]
  vstr s0, [r0,r1] // disassembles as vstr s0, [r0]
  bx lr
  .end

The output from the arm-none-eabi-objdump -d obj/test-s.o command is:

Disassembly of section .text:

00000000 <test>:
    0: ed90 0a00 vldr s0, [r0]
    4: ed80 0a00 vstr s0, [r0]
    8: 4770 bx lr
    a: bf00 nop

This is using arm-none-eabi-gcc-cs-12.2.0-1.fc36.x86_64